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[Embeded-SCM Develop] verilog.HDL.examples

Description: 许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等-many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.
Platform: | Size: 188277 | Author: 张驰 | Hits:

[Other resource] adc

Description: 编写verilog代码 利用实验箱上的A/D芯片完成模数转换。输入电压由实验箱提供，其幅值在0~5V间变化，由电位器控制。输出信号显示输入的模拟电压值，由数码管显示为2位BCD码的形式。
Platform: | Size: 22228 | Author: Ericwhu | Hits:

[Other resource] ADC

Description: 用verilog编程实现的基于FPGA的AD数据采集程序
Platform: | Size: 499824 | Author: 张西贝 | Hits:

[VHDL-FPGA-Verilog] modulator

Description: 运用FPGA控制AD9957的操作，调试过，运用VERILOG HDL编写-Use FPGA to control the operation of AD9957, debugging, and use the preparation of VERILOG HDL
Platform: | Size: 904192 | Author: px99 | Hits:

[VHDL-FPGA-Verilog] xapp355

Description: Serial ADC Interface write in VHDL based on xilinx cpld
Platform: | Size: 33792 | Author: jiang | Hits:

[VHDL-FPGA-Verilog] ADC_16bit

Description: 16位ADCverilog hdl 代码-16 ADCverilog hdl code
Platform: | Size: 1024 | Author: skdk | Hits:

[VHDL-FPGA-Verilog] sample8

Description: 运行在FPGA上的Verilog程序，实现对ADC的控制。在控制模块提供的时钟及控制信号下工作，完成模拟信号的量化和编码。
Platform: | Size: 300032 | Author: 叶开 | Hits:

[VHDL-FPGA-Verilog] ADCtest

Description: 利用Verilog HDL对AD7705进行控制ADC采样，实验室师兄的-Using Verilog HDL to the AD7705 control ADC sampling, laboratory师兄the
Platform: | Size: 589824 | Author: ticklay | Hits:

[VHDL-FPGA-Verilog] ADC0832_test

Description: ADC0832是一个8-bit的ADC转化芯片，工作频率为250Khz，最大频率可达400Khz，转化通道有两个，输入电压可分有单端或差分形式。本测试使用单端电压输入形式，从昔年的CH0输入电压，使用Xilinx XC3S200AN开发板，并且使用Xilinx ise工具中的ChipScope工具来查看转化后的DO数据是否正确。经验证，输入电压范围是0V--5.5V,当电压达到5.5V时，满刻度.-ADC0832 is an 8-bit conversion of the ADC chip, the working frequency of 250Khz, the maximum frequency of up to 400Khz, into two channels, the input voltage can be divided into single-ended or differential form. This test used the form of single-ended voltage input, from the previous years of the CH0 input voltage, the use of Xilinx XC3S200AN development board, Xilinx ise tools and use of ChipScope tool to see into the post-DO data is correct. Validated, input voltage range is 0V- 5.5V, when the voltage reaches 5.5V, the full-scale.
Platform: | Size: 3628032 | Author: zhangjiansen | Hits:

[VHDL-FPGA-Verilog] verilogsigma-deltaadc

Description: 用verilog编写的sigma-deltaADC的源程序。-code of verilog for sigma delta ADC
Platform: | Size: 4096 | Author: 刘晓志 | Hits:

[VHDL-FPGA-Verilog] TCL2543

Description: 基于FPGA的TLC2543控制器,采用状态进行控制ADC进行转换-The TLC2543 controller based on FPGA, using state control of ADC conversion
Platform: | Size: 286720 | Author: 555 | Hits:

[VHDL-FPGA-Verilog] adc_spi

Description: dsp通过SPI接口数据采集 sigma-delta ADC采集程序-dsp through the SPI interface, data acquisition sigma-delta ADC acquisition program
Platform: | Size: 8192 | Author: xingtian | Hits:

[VHDL-FPGA-Verilog] AD0819

Description: 利用verilog语言实现对AD0819的模数转换控制，源代码工程文件-Verilog language used on the AD0819' s ADC control, source code project files
Platform: | Size: 98304 | Author: lifejoy | Hits:

[VHDL-FPGA-Verilog] TERASIC_AUDIO

Description: 友晶提供的Audio的IP核。这个IP核提供了Verilog的硬件部分源码和相应的HAL驱动程序。-Audio provided by Friends of Crystal' s IP core. The IP core provides a Verilog hardware part of the source and the corresponding HAL driver.
Platform: | Size: 125952 | Author: changjiang | Hits:

[Other] part1_2.tar

Description: this a 10bit 80MSample/sec SAR ADC with offset cancellation capability (implemented in verilog)-this is a 10bit 80MSample/sec SAR ADC with offset cancellation capability (implemented in verilog)
Platform: | Size: 288768 | Author: meteora | Hits:

[VHDL-FPGA-Verilog] AD7938controllor-VHDL

Description: VHDL语言的有限状态机法控制8位/12位自动转换通道模数转换器AD7938-VHDL, FSM method to control 8-bit/12-bit ADC AD7938 auto-conversion channel
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] hsadc

Description: ADC ADS62P49 It is TI adc verilog source code for
Platform: | Size: 2127872 | Author: anil | Hits:

[VHDL-FPGA-Verilog] ADC-

Description: it is the document & source code in verilog of adc using sparten 3e fpga kit
Platform: | Size: 721920 | Author: kamlesh | Hits:

[VHDL-FPGA-Verilog] adc

Description: 用verilog实现TLC549——AD采集实验，采集完的数送给数码管显示-TLC549- AD Acquisition experimental collection finished with verilog number sent to the digital tube display
Platform: | Size: 595968 | Author: 蒋亮 | Hits:

[Program doc] berckley pipeline adc verilog model

Description: berckley pipeline adc verilog model
Platform: | Size: 1457664 | Author: beidawuxi123 | Hits:
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